1. Field of the Invention
The present invention relates to a data processing system such as a microcomputer, having a serial interface.
2. Description of Related Art
In a conventional data processing system including a microprogram controlled central processing unit (CPU), an interrupt controller (INTC) and a serial interface, it is in many cases that a simple input/output processing such as a serial data sending/receiving is performed by a macroservice function, not by a programmed processing based on a vector interrupt. Here, the vector interrupt is that a program counter (PC) and a program status word (PSW) is automatically saved to a stack memory and an operation is branched into an interrupt processing routine so as to execute a predetermined program written by macro-instructions. On the other hand, the macroservice is that, in response to an interrupt request, a data transfer is performed, by a hardware, between a special function register and a memory space. For example, if a macroservice request is generated, the CPU temporarily stops execution of the program, and automatically carries out a data transfer of one or two bytes between the special function register and the memory. When the data transfer is completed, the interrupt request flag is reset, and the CPU resumes the execution of the program. Alternatively, after the data transfers of the number set in a macroservice counter have been performed, the vector interrupt request is generated.
Differently from other interrupt processings, this macroservice processing does not activate an interrupt processing program, but automatically performs a predetermined processing stored in a microprogram ROM (read only memory). Accordingly, a series of operations including the branching to the interrupt service routine, the saving and returning of the registers, the returning from the interrupt service routine, are not performed. Accordingly, it is possible to elevate the service time of the CPU and to reduce the number of steps in the program.
Referring to FIG. 1, there is shown a block diagram of one typical example of the conventional data processor having a serial interface. The shown data processor includes a CPU 1, an interrupt controller (INTC) 2 and a serial interface 3, which are interconnected through an internal bus 4.
In response to a transmission start signal ST from the CPU 1, data on the internal bus 4 is set into the serial interface 3, and thereafter, the data is serially transferred from an output terminal OUT. If the data to be sent in the serial interface 3 becomes empty, a request signal REQ is generated in the serial interface 3 and sent to the interrupt controller 2.
If the interrupt controller 2 receives the request signal REQ from the serial interface 3, the interrupt controller 2 discriminates the priority order Of the interrupt and the status of the interrupt mask. If it is permissible to acknowledge the request signal REQ, the interrupt controller 2 asynchronously outputs an interrupt request signal INTREQ to the CPU 1.
If the CPU 1 receives the interrupt request signal INTREQ from the interrupt controller 2, the CPU 1 executes a processing in accordance with the value MS/INT of a status flag register 2A in the interrupt controller 2. If MS/INT=1, a microprogram for the macroservice is activated so as to execute the macroservice function processing. If MS/INT=0, the vector interrupt processing is executed. Incidentally, the CPU 1 can rewrite the status flag register 2A by outputting a signal WR to the interrupt controller 2. The CPU includes a macroservice counter. (MSC) 1A, which can be formed by utilizing for example an internal RAM (random access memory).
Referring to FIG. 2, there is shown a detailed circuit diagram of the serial interface 3. In FIG. 2, in response to the transmission start signal ST from the CPU 1, a transmission shift register 31 of for example eight bits is set with the data on the internal bus 4 which is also of eight bits in this case. The 8-bit data stored in the shift register 31 is shifted in response to a serial clock CLK so as to be serially outputted through an output buffer 32 form the output terminal OUT. Thus, a serial transmission is carried out.
All stages or bits of the transmission shift register 31 are coupled to a transmission end detection circuit 33, which is configured to detect whether or not the transmission shift register 31 becomes empty, for the purpose of detecting completion of the transmission of the 8-bit data. This transmission end detection circuit 33 generates the above mentioned request signal REQ. For example, this transmission end detection circuit 33 can be constituted of an eight-input exclusive-OR circuit.
Now, the macroservice function of the data processor shown in FIG. 1 including the serial interface 3 shown in FIG. 2 will be described with reference to FIG. 3 illustrating the flow of operation.
At the time of serially transmitting a plurality of bytes of data, the number of serial transmissions is firstly set into the macroservice counter 1A which is managed in the course of the macroservice processing, in order to ensure that a predetermined number of macroservices are performed. In addition, the value MS /INT of the status flag register 2A in the interrupt controller 2 is previously set to "1".
When the transmission shift register 31 becomes empty, the request signal REQ is generated by the serial interface 3, and then, the interrupt request signal INTREQ is generated by the interrupt controller 2. Therefore, the CPU 1 executes the macroservice function processing in accordance with the value MS/INT(=1) of the status flag register 2A in the interrupt controller 2. Namely, the CPU transfers one byte of data to be transmitted, through the internal bus 4 to the transmission shift register 31, and further decrements the macroservice counter 1A by one. The data set into the transmission shift register 31 is serially outputted from the output terminal OUT in synchronism with the serial clock CLK. When the transmission shift register 31 becomes empty again, the request signal REQ is generated by the serial interface 3, again.
In the above mentioned manner, a series of bytes of data to be transmitted are transferred continuously. When a last byte of data of the predetermined number of bytes of data to be transmitted has been transferred to the transmission shift register 31, the value MSC of the macroservice counter 1A is brought to 0 (zero). In response to MSC=0, the CPU 1 rewrites the value MS/INT of the status flag register 2A in the interrupt controller 2 to 0 (zero) by the signal WR. As a result, the macroservice function processing is completed.
In the above mentioned condition, if the transmission shift register 31 becomes empty, the request signal REQ is generated by the serial interface 3. At this time, if no interrupt signal is generated by the other interrupt sources, the interrupt request signal INTREQ is generated by the interrupt controller 2, and sent to the CPU 1. Since the value MS/INT of the status flag register 2A in the interrupt controller 2 is 0 (zero) which designates the vector interrupt, the CPU 1 activates a microprogram for the vector interrupt, so that a vector interrupt processing program is activated.
However, when new data to be transmitted is transferred to the transmission shift register 31 in the vector interrupt processing just after the completion of the macroservice function processing, the serial transmission of the last byte of data transferred to the transmission shift register 31 at the end of the macroservice function processing has not yet been completed, since the processing speed of the CPU 1 (for example, on the order of MHz) is greatly different from the serial transmission speed of the serial interface 3 (for example, on the order of KHz).
In order to overcome this inconvenience, it is the prior art manner to transfer the new data to be transmitted to the transmission shift register 31 with a sufficient delay time, or to inhibit the transfer of the data to the transmission shift register 31 in the course of the vector interrupt processing. In other words, in a special case of changing from the macroservice function processing to the vector interrupt processing, a mismatching occurs between the serial transmission status of the transmission shift register 31 and the software processing of the CPU.